Design of 3x3 router using buffer resizing technique for 1d and 2d NoC architectures

An FPGA based, Reconfigurable 3x3 router for both 1-D and 2-D network on chip architectures design is proposed. The design is highly scalable and exploits the features provided by any standard FPGA platform and can be easily ported to an ASIC or any other FPGA platform. These routers are reconfigurable and they are capable of transmitting both 1D and 2D packets throughout the network, this reduces the power consumption when communication pattern changes. In general these routers occupy most of the area in the network, which however reduces the performance and increases the latency. The latency in transmitting packets is decreases with increasing the depth of the buffers; this consumes more area in the routers. The reconfigurable router proposed here uses “buffer resizing technique” which reduces the depth of the static buffers present in the router. This reduces the area of the router without increasing the latency in the network. The results prove the proposed design is robust and cost effective. Each router consumes a mere 3.689W power in the worst case while achieving high clock rates of 344.270MHz easily on the target FPGA device post design synthesis and emulation.